1. Field of the Invention
The present invention is directed to a method for manufacturing a semiconductor device, and in particular to a method for forming an interconnection in a semiconductor device.
2. Background of the Related Art
FIG. 1 illustrates a crystal structure of a hydrogen silsesquoxane (HSQ) which is a general insulation film with a low dielectric constant. As shown in FIG. 1, the insulation material with the low dielectric constant has a low volume density of atoms. However, if the insulation material is exposed to heat and plasma during a processing step, the insulation material is damaged, and thus cannot maintain its original profile.
FIGS. 2A to 2F are cross-sectional views illustrating a related art method for forming an interconnection in a semiconductor device using HSQ.
As depicted in FIG. 2A, a first insulation layer 2 with a first trench 2A is formed on a semiconductor substrate 1. The substrate 1 is a silicon wafer on which a semiconductor device has been manufactured, but not the interconnections. The upper portion of the substrate 1 is mostly planarized by chemical mechanical polishing or etchback. The first insulation film 2 is composed of layer insulation materials, such as BPSG, SOG and PE-TEOS.
If the first insulation layer 2 has inferior mechanical properties, such that it is difficult to carry out chemical mechanical polishing on a metal to be deposited, an insulation layer (not shown) such as a silicon oxide film may be formed on the first insulation layer 2 to act as an etch stopper during chemical mechanical polishing.
Then, a first barrier metal layer 3 is formed at the upper portion of the first insulation layer 2 and in the first trench 2a. A first metal layer 4 is formed on the first barrier metal layer 3. As a result, the first trench 2a is filled with the first metal layer 4. The first barrier metal layer 3 is one of Ti, Ti/TiN and TiW, and the first metal layer 4 is copper.
As illustrated in FIG. 2B, the first barrier metal layer 3 and the first metal layer 4 are partially removed by chemical mechanical polishing, so that the upper portion of the first insulation layer 2 is exposed, thereby forming a first interconnection layer 5 in the first trench 2a. Then, a second insulation layer 6, a third insulation layer 7 and a fourth insulation layer 8 are formed at the upper portions of the first insulation layer 2 and the first interconnection layer 5. The second insulation layer 6 consists of a silicon nitride which is a metal cap insulation material, the third insulation layer 7 consists of an insulation material with a low dielectric constant, and the fourth insulation layer 8 is composed of a silicon oxide. In general, hydrogen silsesquoxane (HSQ) is employed as the insulation material with the low dielectric constant.
As illustrated in FIG. 2C, portions of the third and fourth insulation layers 7, 8 corresponding to the first interconnection layer 5 are removed by reaction ion etching using a photoresist film pattern (not shown) as a mask. Thus, a second trench 7a is formed in the third insulation layer 7. The second insulation layer 6 functions as the etch stopper during the etching.
As depicted in FIG. 2D, the portion of the second insulation layer 6 exposed by the second trench 7a is removed by reaction ion etching using an oxygen plasma. As a result, the sidewalls of the third insulation layer 7 that are exposed to the second trench 7a are caved. In other words, when the insulation material with the low dielectric constant, such as the HSQ is used as the third insulation layer 7, hydrogen elements in the HSQ and oxygen elements in the oxygen plasma are combined, thereby caving the sidewalls of the third insulation layer 7.
As illustrated in FIG. 2E, a second barrier metal layer 9 is formed at the upper portion of the fourth insulation layer 8 and in the second trench 7a. A second metal layer 10 is then formed on the second barrier metal layer 9. As a result, the second trench 7a is filled with the second metal layer 10. The second barrier metal layer 9 is generally one of Ti, Ti/TiN and TiW. The second metal layer 10 is generally copper.
As depicted in FIG. 2F, the second metal layer 10 is chemically mechanically polished so that the upper portion of the fourth insulation layer 8 is exposed, and thus a second interconnection layer 11 is formed in the second trench 7a. As a result, the second interconnection layer 11 is connected to the first interconnection layer 5. However, a void 12 occurs at the center of the second trench 7a because the third insulation layer 7 is caved. The fourth insulation layer 8 functions as the etch stopper during the chemical mechanical polishing.
The related art method of forming interconnections in the semiconductor device has various disadvantages. For example, as illustrated in FIG. 2D, when the second insulation layer (silicon nitride layer) 6 is partially removed by etching in order to form the interconnection, a bowing occurs, namely the sidewalls of the third insulation layer (HSQ layer) 7 exposed in the second trench 7a are caved. Further, as depicted in FIG. 2E, a void 12 occurs at the center of the second trench 7a because the third insulation layer 7 is caved, thereby reducing the mass productivity and the reliability of the interconnections. Moreover, when the second barrier metal layer 9, as well as the second metal layer 10, are removed by chemical mechanical polishing in order to form the second interconnection layer 11 in the second trench 7a, two kinds of slurries must be used and two process conditions must be applied, thereby complicating the entire manufacturing process.